• DocumentCode
    836103
  • Title

    Scalable techniques for system-level cosimulation and coestimation

  • Author

    Lajolo, M. ; Passerone, C. ; Lavagno, L.

  • Author_Institution
    NEC Labs. America, Princeton, NJ, USA
  • Volume
    150
  • Issue
    4
  • fYear
    2003
  • fDate
    7/18/2003 12:00:00 AM
  • Firstpage
    227
  • Lastpage
    238
  • Abstract
    A system-level design approach that enforces a separation between system behaviour and architecture is presented. The system designer focuses first on system behaviour, then looks for a suitable architecture to implement it, and finally verifies the performance. Techniques and tools are described to accurately evaluate the performance of a system at different levels of abstraction. The evaluation must be done dynamically, in a simulation framework, to capture runtime interaction among tasks and with the environment model. Moreover, it should be fast enough to enable the exploration of several algorithmic and architectural solutions in the search for the best implementation. Tunable models, where the designer can trade accuracy for speed, are essential for this purpose.
  • Keywords
    circuit simulation; digital simulation; hardware-software codesign; performance evaluation; performance; runtime interaction; scalable techniques; system behaviour; system-level coestimation; system-level cosimulation; system-level design approach; tunable models;
  • fLanguage
    English
  • Journal_Title
    Computers and Digital Techniques, IEE Proceedings -
  • Publisher
    iet
  • ISSN
    1350-2387
  • Type

    jour

  • DOI
    10.1049/ip-cdt:20030691
  • Filename
    1250438