DocumentCode :
836160
Title :
Hardware Architecture for High-Performance Regular Expression Matching
Author :
Lee, Tsern-Huei
Author_Institution :
Dept. of Commun. Eng., Nat. Chiao Tung Univ., Hsinchu
Volume :
58
Issue :
7
fYear :
2009
fDate :
7/1/2009 12:00:00 AM
Firstpage :
984
Lastpage :
993
Abstract :
This paper presents a bitmap-based hardware architecture for the Glushkov nondeterministic finite automaton (G-NFA), which recognizes a given regular expression. We show that the inductions of the functions needed to construct the G-NFA can be generalized to include other special symbols commonly used in extended regular expressions such as the POSIX 1003.2 format. Our proposed implementation can detect the ending positions of all substrings of an input string T, which start at arbitrary positions of T and belong to the language defined by the given regular expression. To achieve high performance, the implementation is generalized to the NFA, which processes K symbols in each operation cycle. We provide an efficient solution for the boundary condition when the length of the input string is not an integral multiple of K. Compared with previous designs, our proposed architecture is more flexible and programmable because the pattern matching engine uses memory rather than logic.
Keywords :
finite automata; pattern matching; Glushkov nondeterministic finite automaton; POSIX 1003.2 format; bitmap-based hardware architecture; boundary condition; high performance regular expression matching; input string; pattern matching engine; Automata; Doped fiber amplifiers; Engines; Hardware; Inspection; Intrusion detection; Logic design; Pattern matching; Programmable logic arrays; Security; Hardware acceleration; content inspection; hardware acceleration; nondeterministic finite automaton; regular expression; regular expression.; virus signature;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2008.145
Filename :
4599575
Link To Document :
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