FASTBUS simulation tools

Author

Dean, T.D. ; Haney, M.J.

Author_Institution

SLAC, Stanford Univ., CA, USA

Volume

39

Issue

4

fYear

1992

fDate

8/1/1992 12:00:00 AM

Firstpage

910

Lastpage

914

Abstract

A generalized model of a FASTBUS master is presented. The model is used with simulation tools to aid in the specification, design, and production of FASTBUS slave modules. The model was written in the IEEE standard 1076-1987 hardware description language VHDL. A model of the ATC logic is presented. The models, in conjunction with most commercially available simulators, will perform all of the transactions specified in IEEE standard 960-1989. The master model accepts a stream of high-level commands from an ASCII file to initiate FASTBUS transactions. The high-level command language is based on the FASTBUS standard routines listed in IEEE standard 1177-1989. The designer specifies the FASTBUS cycles to be performed in a language based on the FASTBUS standard routines, and the timing of the simulation is dictated by the behavior of the models

Keywords

digital simulation; nuclear electronics; physics computing; system buses; ASCII file; ATC logic; FASTBUS master; FASTBUS simulation tools; FASTBUS slave modules; FASTBUS standard routines; IEEE standard 1076-1987 hardware description language VHDL; IEEE standard 1177-1989; IEEE standard 960-1989; high-level command language; Command languages; Fastbus; Hardware design languages; Linear accelerators; Predictive models; Production; Programming profession; Protocols; Software performance; Testing;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.159731

Filename

159731