FASTBUS simulation tools

A generalized model of a FASTBUS master is presented. The model is used with simulation tools to aid in the specification, design, and production of FASTBUS slave modules. The model was written in the IEEE standard 1076-1987 hardware description language VHDL. A model of the ATC logic is presented. The models, in conjunction with most commercially available simulators, will perform all of the transactions specified in IEEE standard 960-1989. The master model accepts a stream of high-level commands from an ASCII file to initiate FASTBUS transactions. The high-level command language is based on the FASTBUS standard routines listed in IEEE standard 1177-1989. The designer specifies the FASTBUS cycles to be performed in a language based on the FASTBUS standard routines, and the timing of the simulation is dictated by the behavior of the models