Radiation Hardened PMOS Process with Ion Implanted Threshold Adjust

Radiation effects on MOS devices have been extensively investigated and minimized by processing modifications. Generally, the use of ion implantation through the gate oxide is avoided to ensure gate oxide integrity when fabricating radiation hardened integrated circuits. A p-channel metal gate MOS integrated circuit process (space flight qualified) relying on ion implantation has been developed and evaluated. Ion implantation of boron eleven (B") at 56 KeV is utilized for depletion resistor formation and for adjusting the p-channel enhancement transistor threshold voltage. PMOS large scale integrated (LSI) circuits performed successfully after gamma irradiation of 6×105 rads silicon. Individual hardened p-channel transistors (ion implanted) experienced about 0.5v shift in threshold voltage after this dose. Parameters monitored on an LSI as a function of the integrated dose included gate threshold voltage, count pulse width, power consumption, count rate and shift rate. All parameters exhibited some shift from the initial pre-irradiation values but were well within specified tolerance levels after the 6×105 rad dosage. Subsequent annealing of the irradiated integrated circuits for 24 hours at 250°C N2 restored all chips to their pre-irradiation condition. This paper will present the process modifications, testing and results of our fully ion implanted radiation hard PMOS process.