DocumentCode :
837247
Title :
Combined hardware selection and pipelining in high-performance data-path design
Author :
Note, Stefaan ; Catthoor, Francky ; Goossens, Gert ; De Man, Hugo J.
Author_Institution :
Interuniv. Micro-Electron. Center, Leuven, Belgium
Volume :
11
Issue :
4
fYear :
1992
fDate :
4/1/1992 12:00:00 AM
Firstpage :
413
Lastpage :
423
Abstract :
At the highest abstraction level, the specification of a data path consists of a number of interconnected abstract building blocks and a constraint on the minimal clock frequency. An algorithm which optimally selects hardware blocks for implementing these abstract building blocks is presented. A technique for hierarchical redistribution and insertion of pipeline registers is also presented. Finally, the two optimization tasks are combined. This combination makes the area tradeoff between the cost of additional speedup circuitry and pipeline registers possible. The techniques are based on accurate hierarchical timing models for the hardware blocks. The automation relieves the designer of the numerous, time-consuming critical path verifications and area evaluations that are required to explore the large design space. The implementation of the algorithms has resulted in a CAD tool called HANDEL, embedded in the data-path compiler CHOPIN
Keywords :
circuit layout CAD; logic CAD; pipeline processing; CAD tool; CHOPIN; HANDEL; data-path compiler; data-path design; hardware selection; hierarchical redistribution; hierarchical timing models; interconnected abstract building blocks; net-based algorithm; optimization tasks; pipeline register insertion; pipelining; Clocks; Costs; Design automation; Digital signal processing; Hardware; Integrated circuit interconnections; Network synthesis; Optimization; Pipeline processing; Registers;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.125089
Filename :
125089
Link To Document :
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