DocumentCode
837270
Title
Performance analysis of latency-insensitive systems
Author
Lu, Ruibing ; Koh, Cheng-Kok
Author_Institution
Synopsys Inc., Mountain View, CA, USA
Volume
25
Issue
3
fYear
2006
fDate
3/1/2006 12:00:00 AM
Firstpage
469
Lastpage
483
Abstract
This paper formally models and studies latency-insensitive systems (LISs) through max-plus algebra. We introduce state traces to model behaviors of LISs and obtain a formally proved performance upper bound achievable by latency-insensitive design. An implementation of the latency-insensitive protocol that can provide robust communication through back-pressure is also proposed. The intrinsic performance of the proposed implementation is acquired based on state traces. It is also proved that the proposed implementation can always reach the best performance achievable by latency-insensitive design.
Keywords
algebra; circuit analysis computing; integrated circuit interconnections; integrated circuit modelling; latency-insensitive design; latency-insensitive protocol; latency-insensitive system; max-plus algebra; performance analysis; robust communication; state traces; Algebra; Clocks; Delay estimation; Integrated circuit interconnections; Performance analysis; Protocols; Registers; Robustness; Timing; Upper bound; Back-pressure; latency-insensitive system; max-plus algebra; performance analysis; state trace;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2005.854636
Filename
1597382
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