Title :
Multiobjective hypergraph-partitioning algorithms for cut and maximum subdomain-degree minimization
Author :
Selvakkumaran, Navaratnasothie ; Karypis, George
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of Minnesota, Minneapolis, MN, USA
fDate :
3/1/2006 12:00:00 AM
Abstract :
In this paper, we present a family of multiobjective hypergraph-partitioning algorithms based on the multilevel paradigm, which are capable of producing solutions in which both the cut and the maximum subdomain degree are simultaneously minimized. This type of partitionings are critical for existing and emerging applications in very large scale integration (VLSI) computer-aided design (CAD) as they allow to both minimize and evenly distribute the interconnects across the physical devices. Our experimental evaluation on the International Symposium on Physical Design (ISPD98) benchmark show that our algorithms produce solutions, which when compared against those produced by hMETIS have a maximum subdomain degree that is reduced by up to 36% while achieving comparable quality in terms of cut.
Keywords :
VLSI; circuit complexity; circuit optimisation; integrated circuit design; integrated circuit interconnections; logic CAD; logic partitioning; multichip modules; computer-aided design; interconnect congestion; interconnect distribution; multichip partitioning; multiobjective hypergraph-partitioning algorithm; subdomain-degree minimization; very large scale integration; Algorithm design and analysis; Application software; Computer science; Databases; Design automation; Information retrieval; Iterative algorithms; Minimization methods; Partitioning algorithms; Very large scale integration; Interconnect congestion; multichip partitioning; placement;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2005.854637