Title :
New and improved BIST diagnosis methods from combinatorial Group testing theory
Author :
Kahng, Andrew B. ; Reda, Sherief
Author_Institution :
Eng. & the Dept. of Electr. & Comput. Eng., Univ. of California San Diego, La Jolla, CA, USA
fDate :
3/1/2006 12:00:00 AM
Abstract :
We examine the general problem of built-in-self-test (BIST) diagnosis in digital logic systems. The BIST diagnosis problem has applications that include identification of erroneous test vectors, faulty scan cells, and faulty items. We develop an abstract model of this problem and show a fundamental correspondence to the well-established subject of combinatorial group testing (CGT) (D. Du and F. K. Hwang, Combinatorial Group Testing and Its Applications, 1994). We exploit this new perspective to 1) link existing BIST diagnosis techniques to CGT techniques and provide further insights into existing diagnosis algorithms, 2) improve the performance of diagnosis algorithms, and 3) develop new techniques to address the BIST diagnosis problem. Using the ISCAS´89 benchmarks, we empirically demonstrate the effectiveness of our proposed techniques over existing BIST diagnosis techniques. The vastness of the CGT literature suggests that further improvements from existing research in CGT may be obtained.
Keywords :
VLSI; built-in self test; combinational circuits; fault location; integrated circuit testing; logic testing; VLSI BIST diagnosis; built-in-self-test diagnosis methods; combinatorial group testing theory; digital logic system; erroneous test vector; fault detection; Automatic testing; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Computer science; Fault diagnosis; Hardware; Logic testing; System testing; Fault detection; VLSI BIST diagnosis; testing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2005.854635