Title :
Partitioning algorithms for layout synthesis from register-transfer netlists
Author :
Wu, Allen C H ; Gajski, Daniel D.
Author_Institution :
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
fDate :
4/1/1992 12:00:00 AM
Abstract :
A partitioning methodology that exploits the regularity of register-transfer components is presented, and partitioning algorithms that are used to generate the floor plan are described. The partitioning algorithms not only select the layout style best suited for each component, but also consider critical paths, I/O pin locations, and connections between components. This approach improves the overall area utilization and minimizes the wire length on the critical paths
Keywords :
VLSI; circuit layout CAD; integrated circuit technology; CAD; I/O pin locations; critical paths; floorplan generation; layout synthesis; partitioning algorithms; register-transfer netlists; sliced layout architecture; Counting circuits; Flip-flops; Microprocessors; Multiplexing; Partitioning algorithms; Registers; Routing; Switches; Very large scale integration; Wire;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
