High-level delay test generation for modular circuits

Circuits containing functional blocks (modules) whose implementation details are not available pose major problems for delay fault testing. High-level testing methods are needed, but they often generate excessively large test sets to ensure good realization-independent fault coverage. This paper extends high-level delay fault models to large modular logic circuits by demonstrating that a hierarchical approach to delay test generation for modular circuits is feasible. Module implementation and input pattern pair requirements for robust delay testing are proposed along with a new fault model, the module path delay fault (MPDF) model. A test generation program called Module PATH delay test generator for MPDFs is presented, which exploits binary decision diagrams to increase its efficiency. Experimental results evaluating the proposed technique are presented, which show that it achieves a significant reduction in test set size compared to nonhierarchical approaches.