Crosstalk tolerant latch circuit

The authors present a D-latch sequential circuit that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. For these lines the noise tolerance overruns the power supply voltage (V_dd). In the fraction of the tolerance range with the highest level of noise the circuit becomes a dynamic latch preserving the circuit from the propagation of errors. The circuit and the design rules presented, are oriented to VLSI circuit design in which crosstalk interferences might be foreseen