Characterization of the parasitic bipolar amplification in SOI technologies submitted to transient irradiation

Author

Ferlet-Cavrois, V. ; Marcandella, C. ; Giraud, G. ; Gasiot, G. ; Colladant, T. ; Musseau, O. ; Fenouillet, C. ; du Port de Poncharra, J.

Author_Institution

CEA/DAM-Ile de France, Bruyeres-le-Chatel, France

Volume

49

Issue

3

fYear

2002

fDate

6/1/2002 12:00:00 AM

Firstpage

1456

Lastpage

1461

Abstract

The parasitic bipolar amplification of silicon on insulator (SOI) devices is analyzed as a function of the technology integration from 0.8 μm down to 0.1 μm. Experiments and simulations show that the bipolar gain does not increase with technology downscaling. The body tie efficiency, to reduce the bipolar amplification, is measured on both transistors and circuits. Implications on the dose rate hardness are deduced on registers with and without body ties as a function of the SOI technology integration.

Keywords

amplifiers; bipolar transistors; nuclear electronics; radiation hardening (electronics); silicon-on-insulator; 0.8 to 0.1 micron; SOI technologies; bipolar gain; body tie efficiency; dose rate hardness; parasitic bipolar amplification; silicon-on-insulator devices; transient irradiation; transistors; Bipolar transistor circuits; Bipolar transistors; Circuit simulation; Contacts; Integrated circuit measurements; Isolation technology; MOSFETs; Registers; Silicon on insulator technology; Voltage;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2002.1039683

Filename

1039683