Title :
Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study
Author :
Rebaudengo, M. ; Reorda, M. Sonza ; Violante, M. ; Nicolescu, B. ; Velazco, R.
Author_Institution :
Dipt. Automatica e Informatica, Politecnico di Torino, Italy
fDate :
6/1/2002 12:00:00 AM
Abstract :
In this paper, two low-cost solutions devoted to provide processor-based systems with error-detection capabilities are compared. The effects of single event upsets (SEUs) and single event transients (SETs) are studied through simulation-based fault injection. The error-detection capabilities of a hardware-implemented solution based on parity code are compared with those of a software-implemented solution based on source-level code modification. Radiation testing experiments confirmed results obtained by simulation.
Keywords :
error detection; fault simulation; microprocessor chips; radiation hardening (electronics); error detection mechanism; microprocessor; parity code; radiation testing; simulation-based fault injection; single event transient; single event upset; source-level code; Application software; Circuit faults; Error correction; Fault detection; Hardware; Logic; Microprocessors; Single event transient; Single event upset; Testing;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2002.1039689
