Title :
Design for testability and built-in self test: a review
Author :
Nagle, H. Troy ; Roy, Subhash C. ; Hawkins, Charles F. ; McNamer, Michael G. ; Fritzemeier, Ronald R.
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
fDate :
5/1/1989 12:00:00 AM
Abstract :
A summary is presented of a number of design-for-testability (DFT) and built-in self-test (BIST) schemes that can be used in modern VLSI circuits. The DFT methods presented are used to increase the controllability and observability of the circuit design. Partitioning, bus architectures, test-point insertion, and scan methods are discussed. On-chip hardware for real-time test-pattern generation and data compression are investigated. Several of the DFT methods are then combined to form BIST hardware configurations. Built-in evaluation and self-test (BEST), autonomous test, scan with random inputs, built-in logic block observer (BILBO), partitioning with BEST, test-point insertion with on-chip control, and combined test-pattern generation and data compression (CTGC) are considered. An overview of each BIST scheme is offered.<>
Keywords :
VLSI; integrated circuit testing; VLSI circuits; autonomous test; built-in evaluation; built-in logic block observer; built-in self-test; data compression; design-for-testability; on-chip control; real-time test-pattern generation; test-point insertion; Automatic testing; Built-in self-test; Circuit testing; Controllability; Data compression; Design for testability; Hardware; Logic testing; Observability; Very large scale integration;
Journal_Title :
Industrial Electronics, IEEE Transactions on
