DocumentCode
839282
Title
FRAM design style utilising bit-plate parallel cell architecture
Author
Chung, Yeonbae
Author_Institution
Sch. of Electron. & Electr. Eng., Kyungpook Nat. Univ., Daegu, South Korea
Volume
39
Issue
24
fYear
2003
Firstpage
1706
Lastpage
1708
Abstract
A new FRAM (ferroelectric RAM) design method, utilising a bit-plate parallel cell architecture is presented. This method is effective in reducing circuit and layout overhead caused by the on-pitch plate control circuitry. It also reduces the power consumption in the memory array. Implementation results for a 0.13 μm CMOS technology, 512 kb FRAM prototype show that the memory block area in the proposed architecture is 15.6% less than that of a conventional structure.
Keywords
CMOS memory circuits; SRAM chips; ferroelectric storage; integrated circuit design; low-power electronics; 0.13 micron; 512 kbit; FRAM bit-plate parallel cell architecture; cell capacitor plate; ferroelectric storage integrated CMOS technology; memory array; memory block area; nonvolatile memory; on-pitch plate control circuitry; power consumption reduction;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20031104
Filename
1251529
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