• DocumentCode
    839730
  • Title

    IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level

  • Author

    Cui, Aijiao ; Chang, Chip H. ; Tahar, Sofiene

  • Author_Institution
    Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
  • Volume
    27
  • Issue
    9
  • fYear
    2008
  • Firstpage
    1565
  • Lastpage
    1570
  • Abstract
    This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. The headroom of each disjoint closed cone is evaluated based on its slack and slack sustainability. The notion of slack sustainability in conjunction with an embedding threshold enables closed cones in the critical path to be qualified as watermark hosts if their slacks can be better preserved upon remapping. The watermark is embedded by remapping only qualified disjoint closed cones randomly selected and templates constrained by the signature. This parametric formulation provides a means to capitalize on the headroom of a design to increase the signature length or strengthen the watermark resilience. With the master design, the watermarked design can be authenticated as in nonoblivious media watermarking. Experimental results show that the design can be efficiently marked by our method with low overhead.
  • Keywords
    industrial property; watermarking; IP watermarking; adaptive watermarking technique; disjoint closed cone; incremental technology mapping; logic synthesis level; nonoblivious media watermarking; optimized logic network; slack sustainability; technology mapping; watermark resilience; Bandwidth; Design optimization; Integrated circuit synthesis; Integrated circuit technology; Intellectual property; Logic design; Network synthesis; Protection; Very large scale integration; Watermarking; Digital watermarking; incremental technology mapping; intellectual property (IP) protection (IPP); logic synthesis;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2008.927732
  • Filename
    4603076