Title :
Congestion-Constrained Layer Assignment for Via Minimization in Global Routing
Author :
Tsung-Hsien Lee ; Ting-Chi Wang
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu
Abstract :
In this paper, we study the problem of layer assignment for via minimization, which arises during multilayer global routing. In addressing this problem, we take the total overflow and the maximum overflow as the congestion constraints from a given one-layer global routing solution and aim to find a layer assignment result for each net such that the via cost is minimized while the given congestion constraints are satisfied. To solve the problem, we propose a polynomial-time algorithm which first generates a net order and then performs layer assignment one net at a time according to the order using dynamic programming. Our algorithm is guaranteed to generate a layer assignment solution satisfying the given congestion constraints. We used the six-layer benchmarks released from the ISPD´07 global routing contest to test our algorithm. The experimental results show that our algorithm was able to improve the contest results of the top three winners MaizeRouter, BoxRouter, and FGR on each benchmark. As compared to BoxRouter 2.0 and FGR 1.1, which are newer versions of BoxRouter and FGR, our algorithm respectively produced smaller via costs on all benchmarks and half the benchmarks. Our algorithm can also be adapted to refine a given multilayer global routing solution in a net-by-net manner, and the experimental results show that this refinement approach improved the via costs on all benchmarks for FGR 1.1.
Keywords :
circuit optimisation; computational complexity; dynamic programming; minimisation; network routing; BoxRouter; MaizeRouter; congestion constraint; dynamic programming; layer assignment; minimization; multilayer global routing; polynomial-time algorithm; Benchmark testing; Computer science; Costs; Dynamic programming; Nonhomogeneous media; Polynomials; Routing; Very large scale integration; Global routing; layer assignment; physical design; via minimization;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2008.927733