Multilevel logic synthesis using hybrid pass logic and CMOS topologies

Author

Yip, K. ; Al-Khalili, D.

Author_Institution

Synopsys Inc., Mountain View, CA, USA

Volume

150

Issue

5

fYear

2003

Abstract

The development is described of an automated logic synthesis tool, BDDMAPII, which has the capability of utilising a new multilevel mapping algorithm. It has been designed specifically with a reduced cell library consisting of pass transistor multiplexer-based cells in conjunction with traditional CMOS circuits. These cells were developed based on TSMC´s 0.18μ-CMOS technology. A subset of MCNC91 benchmark circuits are used to evaluate the synthesis tool, and the results are compared to those generated by Design Analyzer, a commercial tool from Synopsys Inc. An improvement of an average of 21% in power-delay product was achieved when using the proposed hybrid cell library

Keywords

CMOS logic circuits <multilevel logic synthesis, hybrid pass logic and CMOS topologies>; circuit CAD <multilevel logic synthesis, hybrid pass logic and CMOS topologies>; integrated circuit design <multilevel logic synthesis, hybrid pass logic and CMOS topologies>; logic CAD <multilevel logic synthesis, hybrid pass logic and CMOS topologies>; multivalued logic circuits <multilevel logic synthesis, hybrid pass logic and CMOS topologies>; BDDMAPII; CMOS technology; automated logic synthesis tool; design automation tools; hybrid pass logic; multilevel logic synthesis; multilevel mapping algorithm; multithreshold transistors; pass transistor multiplexer-based cells; power-delay product; reduced cell library;

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings -

Publisher

iet

ISSN

1350-2409

Type

jour

DOI

10.1049/ip-cds:20030407

Filename

1251667