Title :
Efficient algorithm for logic design using multiplexers
Author_Institution :
Defence Electron. Res. Lab., Hyderabad
fDate :
2/4/1988 12:00:00 AM
Abstract :
An algorithmic procedure has been developed for the realisation of any Boolean function F(n) of n variables with a single multiplexer of minimum size. This procedure gives the choice of control variables to be used for the realisation of the function. The algorithm is iterative in nature and very suitable for machine implementation
Keywords :
Boolean functions; logic design; Boolean function; algorithmic procedure; control variables; logic design; machine implementation; multiplexers;
Journal_Title :
Electronics Letters
