DocumentCode
839963
Title
Study of the operation speed of half-micron design rule CMOS ring oscillators
Author
Yoshimi, M. ; Tsuchiya, K. ; Iwase, M. ; Takahashi, M. ; Nishimura, E. ; Suzuki, T. ; Kato, Y.
Author_Institution
VLSI Res. Centre, Toshiba Corp., Kawasaki, Japan
Volume
24
Issue
3
fYear
1988
fDate
2/4/1988 12:00:00 AM
Firstpage
146
Lastpage
147
Abstract
The operation speed of a 73-stage CMOS ring oscillator with 0.5 μm channel lengths has been investigated. By employing a capacitance-reduced structure, gate delays of 47.4 ps and 49.3 ps with and without substrate bias at room temperature, and of 43.0 ps at 77 K, respectively, have been experimentally obtained at a supply voltage of 5 V. From the evaluation of parasitic capacitances, the speed which is achievable by the proper scaling of the device parameters at a half-micron design rule is estimated to be approximately 30 ps
Keywords
CMOS integrated circuits; integrated circuit technology; 0.5 micron; 30 ps; 43.0 ps; 47.4 ps; 49.3 ps; 5 V; 77 K; CMOS ring oscillators; capacitance-reduced structure; channel lengths; gate delays; half-micron design rule; operation speed; parasitic capacitances; scaling; substrate bias; supply voltage;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
Filename
191593
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