Efficient bit-level systolic array implementation of FIR and IIR digital filters

Author

Wang, Chin-Liang ; Wei, Che-Ho ; Chen, Sin-Horng

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Volume

6

Issue

3

fYear

1988

fDate

4/1/1988 12:00:00 AM

Firstpage

484

Lastpage

483

Abstract

Bit-level systolic architectures based on an inner-product computation scheme for finite-impulse response (FIR) and infinite-impulse-response (IIR) digital are presented. The FIR filter structure is optimized in the sense that for a given clock rate, both the utilization efficiency and average throughput are maximized. The IIR filter structure has approximately the same utilization efficiency and throughput rate as previous related techniques for processing a single data stream (channel), but it allows two data streams to be processed concurrently to double the performance. This feature makes the IIR system attractive for use in applications where multiple filtering and particularly bandpass analysis are required

Keywords

VLSI; cellular arrays; digital filters; filtering and prediction theory; FIR filter structure; IIR digital filters; average throughput; bandpass analysis; bit-level systolic array; concurrent processing; data stream; finite-impulse response; infinite-impulse-response; inner-product computation scheme; multiple filtering; utilization efficiency; Band pass filters; Clocks; Digital filters; Filtering; Finite impulse response filter; Hardware; IIR filters; Signal processing; Systolic arrays; Throughput;

fLanguage

English

Journal_Title

Selected Areas in Communications, IEEE Journal on

Publisher

ieee

ISSN

0733-8716

Type

jour

DOI

10.1109/49.1916

Filename

1916