High-Speed Hardware Arbitration Supporting Priorities and Bounded Service Latency

Effective utilization of the available resources in network processors and in modern embedded multicore systems primarily requires advanced hardware-based scheduling techniques to manage increasing arbitration rates. In this scope, this letter presents the architecture and a low-cost ultra high-speed implementation of a novel arbiter. While average response time or service throughput is often an inadequate metric when dealing with strict time constraints, the proposed hardware scheme features an innovative scheduling technique supporting prioritization, while at the same time this arbiter guarantees bounded service latency. Based on a dual priority enforcer scheme, a 64-input scheduler is implemented in a standard 0.13 um CMOS technology making approximately over 200 million scheduling decisions per second.