Due-Date Assignment for Wafer Fabrication Under Demand Variate Environment

Author

Pearn, W.L. ; Chung, S.H. ; Lai, C.M.

Author_Institution

Dept. of Ind. Eng. & Manage., Nat. Chiao Tung Univ., Hsinchu

Volume

20

Issue

2

fYear

2007

fDate

5/1/2007 12:00:00 AM

Firstpage

165

Lastpage

175

Abstract

In the semiconductor industry, dynamic changes in demand force companies to change the product mix frequently and periodically. Assigning tight but attainable due dates is a great challenge under the circumstances that the product mix changes periodically. In this paper, we consider the due-date assignment problem for wafer fabrication and present a due-date assignment model to set manufacturing due dates satisfying the target on-time-delivery rate. The contamination model is applied to tackle the effect of that product mix varies periodically. We demonstrate the effectiveness and accuracy of the proposed model by solving a real-world example taken from a wafer fabrication shop floor in an IC manufacturing factory

Keywords

capacity planning (manufacturing); integrated circuit manufacture; job shop scheduling; time to market; IC manufacturing factory; contamination model; demand variate environment; due-date assignment; manufacturing due dates; product mix; semiconductor industry; wafer fabrication; Application specific integrated circuits; Contamination; Cost function; Dispatching; Electronics industry; Fabrication; Integrated circuit modeling; Pulp manufacturing; Semiconductor device modeling; Virtual manufacturing; Contamination model; due-date assignment; flow time; product mix; wafer fabrication;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/TSM.2007.895215

Filename

4182437