Modified Model for Settling Behavior of Operational Amplifiers in Nanoscale CMOS

Author

Rezaee-Dehsorkh, Hamidreza ; Ravanshad, Nassim ; Lotfi, Reza ; Mafinezhad, Khalil

Author_Institution

Dept. of Electr. Eng., Ferdowsi Univ. of Mashhad, Mashhad

Volume

56

Issue

5

fYear

2009

fDate

5/1/2009 12:00:00 AM

Firstpage

384

Lastpage

388

Abstract

An accurate time-domain model for the settling behavior of folded-cascode operational amplifiers is presented. Using a velocity-saturation model for MOS transistors makes the proposed model suitable for nanoscale CMOS technologies. Both linear and nonlinear settling regimes and their combination are considered. Transistor-level HSPICE simulation results of a fully differential single-stage folded-cascode amplifier using BSIM4v3 models of a standard 90-nm CMOS process are presented to verify the accuracy of the proposed models.

Keywords

CMOS analogue integrated circuits; SPICE; integrated circuit modelling; nanoelectronics; operational amplifiers; time-domain analysis; BSIM4v3 model; MOS transistor; folded-cascode operational amplifier; fully differential single-stage folded-cascode amplifier; nanoscale CMOS technology; settling behavior; size 90 nm; time-domain model; transistor-level HSPICE simulation; velocity-saturation model; Integrated circuit modeling; nanoscale CMOS; operational amplifiers (opamps); settling behavior; velocity saturation;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2009.2019169

Filename

4912332