• DocumentCode
    841630
  • Title

    Testing defects in scan chains

  • Author

    Sachdev, Manoj

  • Author_Institution
    VLSI Design Autom. & Test, Philips Res. Lab., Eindhoven, Netherlands
  • Volume
    12
  • Issue
    4
  • fYear
    1995
  • Firstpage
    45
  • Lastpage
    51
  • Abstract
    Applying scan-based DFT, I/sub DDQ/ testing, or both to sequential circuits does not ensure bridging-fault detection, which depends on the resistance of the fault and circuit level parameters. With a "transparent" scan chain, however, the tester can use both methods to detect manufacturing process defects effectively-including difficult-to-detect shorts in the scan chain. The author presents a strategy for making the scan chain transparent. The test complexity of such a chain is very small, regardless of the number of flip-flops it contains.
  • Keywords
    computational complexity; logic testing; sequential circuits; I/sub DDQ/ testing; bridging-fault detection; difficult-to-detect shorts; manufacturing process defects; scan chains; scan-based DFT; sequential circuits; test complexity;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.491237
  • Filename
    491237