Title :
Three-step heuristic algorithm for optimal PLA column folding
Author :
Yang, Ysung-Yu ; Kyung, Chong-Min
Author_Institution :
Dept. of Electr. Eng., Korea Advanced Inst. of Sci. & Technol., Seoul
fDate :
8/18/1988 12:00:00 AM
Abstract :
A three-step heuristic algorithm for PLA column folding is presented, which is significantly faster than the earlier works and provides nearly optimal results. The three steps are: (i) min-cut partition of vertices in the column intersection graph; (ii) determination of product order using Fiduccia´s min-net cut algorithm; and (iii) head-tail pairing for deciding column folding pairs
Keywords :
cellular arrays; graph theory; integrated logic circuits; logic design; PLA column folding; column folding pairs; column intersection graph; fast near optimal algorithm; head-tail pairing; logic design; min-cut partition; min-net cut algorithm; programmable logic array; three-step heuristic algorithm;
Journal_Title :
Electronics Letters
