Time-domain characterization of interconnect discontinuities in high-speed circuits

Experimental techniques to characterize typical interconnect discontinuities such as bends and steps, based on time-domain reflection (TDR) measurements, are formulated. These interconnect discontinuities are characterized in terms of general lumped/distributed circuit models which are compatible with CAD simulation tools such as SPICE. The results for the model element values are shown to be consistent with frequency-domain lumped equivalent models for microstrips derived from S-parameter measurements and electromagnetic computations based on the excess inductance and capacitance concepts. The models are also validated by simulating their step response on SPICE and comparing them with the TDR data