Title :
A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver
Author :
van Veldhoven, Robert H.M.
Author_Institution :
Philips Res. Labs., Eindhoven, Netherlands
Abstract :
Time jitter in continuous-time ΣΔ modulators is a known limitation on the maximum achievable signal-to-noise-ratio (SNR). Analysis of time jitter in this type of converter shows that a switched-capacitor (SC) feedback digital-to-analog converter (DAC) reduces the sensitivity to time jitter significantly. In this paper, an I and Q continuous-time fifth-order ΣΔ modulator with 1-bit quantizer and SC feedback DAC is presented, which demonstrates the improvement in maximum achievable SNR when using an SC instead of a switched-current (SI) feedback circuit. The modulator is designed for a GSM/CDMA2000/UMTS receiver and achieves a dynamic range of 92/83/72 dB in 200/1228/3840 kHz, respectively. The intermodulation distance IM2, 3 is better than 87 dB in all modes. Both the I and Q modulator consumes a power of 3.8/4.1/4.5 mW at 1.8 V. Processed in 0.18-μm CMOS, the 0.55-mm2 integrated circuit includes a phase-locked loop, two oscillators, and a bandgap.
Keywords :
3G mobile communication; capacitors; code division multiple access; digital-analogue conversion; jitter; phase locked loops; phase locked oscillators; radio receivers; sigma-delta modulation; transceivers; 0.18-μm CMOS; 0.55-mm2 integrated circuit; 1-bit quantizer; 1.8 V; 1228 kHz; 200 kHz; 3.8 mW; 3840 kHz; 4.1 mW; 4.5 mW; 72 dB; 83 dB; 87 dB; 92 dB; CDMA2000; EDGE; GSM; GSM-EDGE/CDMA2000/UMTS receiver; IF conversion; SC feedback DAC; UMTS; bandgap; digital-to-analog converter; fifth-order ΣΔ modulator; intermediate frequency; intermodulation distance IM2; maximum achievable signal-to-noise-ratio; mobile communication; oscillators; phase-locked loop; reduced jitter sensitivity; sigma-delta analog-to-digital converter; sigma-delta modulator; switched-capacitor feedback DAC; switched-current feedback circuit; telecommunication receiver; time jitter analysis; time jitter sensitivity; triple-mode continuous-time ΣΔ modulator; 3G mobile communication; Digital-analog conversion; Dynamic range; Feedback circuits; GSM; Jitter; Phase modulation; Signal to noise ratio; Switching circuits; Switching converters;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2003.819165
