DocumentCode :
842149
Title :
A second-order semidigital clock recovery circuit based on injection locking
Author :
Ng, Hiok-Tiaq ; Farjad-Rad, Ramin ; Lee, M-J Edward ; Dally, William J. ; Greer, Trey ; Poulton, John ; Edmondson, John H. ; Rathi, Rohit ; Senthinathan, Ramesh
Author_Institution :
Velio Commun. Inc., Milpitas, CA, USA
Volume :
38
Issue :
12
fYear :
2003
Firstpage :
2101
Lastpage :
2110
Abstract :
A compact (1 mm × 160 μm) and low-power (80-mW) 0.18-μm CMOS 3.125-Gb/s clock and data recovery circuit is described. The circuit utilizes injection locking to filter out high-frequency reference clock jitter and multiplying delay-locked loop duty-cycle distortions. The injection-locked slave oscillator output can have its output clocks interpolated by current steering the injecting clocks. A second-order clock and data recovery is introduced to perform the interpolation and is capable of tracking frequency offsets while exhibiting low phase wander.
Keywords :
CMOS integrated circuits; audio-frequency oscillators; clocks; delay lock loops; jitter; phase locked loops; transceivers; 1 mm; CMOS clock; clock multiplication; current steering; data recovery circuit; delay-locked loop duty-cycle distortion multiplication; frequency acquisition; frequency offset tracking; frequency tracking; high-frequency reference clock jitter filtering; high-speed transceivers; injection locking; injection-locked slave oscillator output; multiplying delay-locked loop; output clock interpolation; phase interpolation; phase wander; second-order semidigital clock recovery circuit; Circuits; Clocks; Delay; Filtering; Frequency; Injection-locked oscillators; Interpolation; Jitter; Tracking loops; Transceivers;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2003.818576
Filename :
1253857
Link To Document :
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