• DocumentCode
    842223
  • Title

    Aluminum-germanium-copper multilevel damascene process using low-temperature reflow sputtering and chemical mechanical polishing

  • Author

    Kikuta, Kuniko ; Hayashi, Yoshihiro ; Nakajima, Tutomu ; Harashima, Keiichi ; Kikkawa, Takamaro

  • Author_Institution
    ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
  • Volume
    43
  • Issue
    5
  • fYear
    1996
  • fDate
    5/1/1996 12:00:00 AM
  • Firstpage
    739
  • Lastpage
    745
  • Abstract
    A low-temperature multilevel aluminum-germanium-copper (Al-Ge-Cu) damascene technology was developed using reflow sputtering and chemical mechanical polishing (CMP). The maximum processing temperature for the fabrication of multilevel interconnections could be reduced to 420°C using Al-1%Ge-0.5%Cu, whereas the conventional reflow temperature was not less than 500°C. No degradation due to reflow heat cycles was observed in terms of Al-Ge-Cu wiring resistance. Electromigration test results indicated that the mean time to failure (MTTF) of Al-1%Ge-0.5%Cu was longer than 10 years at the operating condition, which was equivalent to that of Al-1%Si-0.5%Cu. The Al-1%Ge-0.5%Cu triple-level interconnection was fabricated using reflow sputtering to fill vias and wiring trenches and subsequent CMP for Al-Ge-Cu films
  • Keywords
    ULSI; aluminium alloys; copper alloys; electromigration; germanium alloys; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit testing; polishing; sputter deposition; wiring; 420 degC; AlGeCu; IC metallisation; MTTF; ULSI; chemical mechanical polishing; electromigration test results; low-temperature reflow sputtering; maximum processing temperature; mean time to failure; multilevel damascene process; multilevel interconnections; operating condition; reflow heat cycles; triple-level interconnection; via filling; wiring resistance; wiring trenches; Chemical technology; Chemical vapor deposition; Etching; Fabrication; Integrated circuit interconnections; Plasma temperature; Silicon compounds; Sputtering; Ultra large scale integration; Wiring;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.491250
  • Filename
    491250