• DocumentCode
    842253
  • Title

    Design of multioperand carry-save adders for arithmetic modulo (2n+1)

  • Author

    Skavantzos, A.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA
  • Volume
    25
  • Issue
    17
  • fYear
    1989
  • Firstpage
    1152
  • Lastpage
    1153
  • Abstract
    The author presents the design of a multioperand adder for arithmetic modulo (2n+1). The adder uses the carry-saving approach and mainly consists of a group of full adders operating in parallel.
  • Keywords
    adders; carry logic; logic circuits; logic design; arithmetic modulo; carry-save adders; logic design; multioperand adder; parallel full adders;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19890773
  • Filename
    41924
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=842253