Title :
Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization
Author :
Moreinis, Michael ; Morgenshtein, Arkadiy ; Wagner, Israel A. ; Kolodny, Avinoam
Author_Institution :
Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa
Abstract :
Logic gates as repeaters (LGRs)-a methodology for delay optimization of CMOS logic circuits with resistance-capacitance (RC) interconnects is described. The traditional interconnect segmentation by insertion of repeaters is generalized to segmentation by distributing logic gates over interconnect lines, reducing the number of additional, logically useless inverters. Expressions for optimal segment lengths and gate scaling are derived. Considerations are presented for integrating LGR into a VLSI design flow in conjunction with related methods. Several logic circuits have been implemented, optimized and verified by LGR. Analytical and simulation results were obtained, showing significant improvement in performance in comparison with traditional repeater insertion, while maintaining low complexity and small area
Keywords :
CMOS logic circuits; VLSI; delays; logic gates; repeaters; timing; CMOS logic circuits; VLSI design flow; delay optimization; gate scaling; logic gate repeaters; optimal segment lengths; resistance-capacitance interconnects; timing optimization; CMOS logic circuits; Delay; Integrated circuit interconnections; Logic circuits; Logic gates; Optimization methods; Pulse inverters; Repeaters; Timing; Very large scale integration; Delay; interconnect; logic; repeaters; timing optimization;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2006.886400
