Neutron Irradiation for Prevention of Latch-Up in MOS Integrated Circuits

Bulk silicon integrated circuits can exhibit latch-up effects which arise from regenerative switching in the parasitic bipolar transistors inherent in the complex circuit configurations. This is especially true for bulk CMOS integrated circuits in which parasitic vertical NPN and lateral PNP bipolars are connected in an SCR fashion. One method for preventing latch-up is lifetime control utilizing neutron irradiation. This work characterizes the long-term annealing of neutron irradiation induced changes in the parasitic bipolar gains of MOS/LSI integrated circuits. A theoretical model, which fits both isothermal and isochronal annealing data, is used to characterize the annealing. Using this model, a procedure has been established for neutron irradiation of LSI integrated circuits which will guarantee that latch-up will not occur during the normal lifetime of the circuits. A detailed discussion of the procedure employed for neutron irradiation of integrated circuits is given, and the results of this procedure applied to several thousand MSI and LSI circuits are described.