• DocumentCode
    842476
  • Title

    Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation

  • Author

    Yung-Chieh Lin ; Feng Lu ; Kwang-Ting Cheng

  • Volume
    26
  • Issue
    5
  • fYear
    2007
  • fDate
    5/1/2007 12:00:00 AM
  • Firstpage
    932
  • Lastpage
    942
  • Abstract
    In this paper, we propose two fault-diagnosis methods for improving multiple-fault diagnosis resolution. The first method, based on the principle of single-fault activation and single-output observation, employs a new circuit transformation technique in conjunction with the use of a special type of diagnostic test pattern, named single-observation single-location-at-a-time (SO-SLAT) pattern. Given a list of candidate suspects (which could be stuck-at, transition, bridging, or other faults obtained by any existing diagnosis method), we generate a set of SO-SLAT patterns, each of which attempts to activate only one fault in the list and propagate its effects only to a specific observation point. Observing the responses of the circuit under diagnosis to the SO-SLAT patterns helps more precisely determine whether each fault suspect is a true or false candidate. The method can tolerate most of the timing hazards for a more accurate diagnosis of failures caused by timing faults. The second method generates and applies limited-cycle sequential tests, based on a Boolean satisfiability solver, to identify multiple defective signals which can jointly explain the circuit´s faulty behavior. These two methods can be applied independently and/or jointly after any existing state-of-the-art diagnosis process to further improve the diagnosis resolution. The experimental results demonstrate the effectiveness of the proposed methods for diagnosing multiple faults, including timing faults
  • Keywords
    Boolean functions; VLSI; fault diagnosis; integrated circuit testing; Boolean satisfiability; VLSI; adaptive diagnostic test; multiple fault diagnosis; pattern generation; very large scale integration; Circuit faults; Circuit testing; Fault diagnosis; Hazards; Sequential analysis; Signal generators; Signal processing; Signal resolution; Test pattern generators; Timing; Boolean satisfiability; diagnosis; testing; very large scale integration (VLSI);
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2006.884486
  • Filename
    4193569