• DocumentCode
    842495
  • Title

    Efficient Timing Analysis With Known False Paths Using Biclique Covering

  • Author

    Shuo Zhou ; Bo Yao ; Hongyu Chen ; Yi Zhu ; Hutton, M. ; Collins, Thomas ; SRINIVASAN, SUDARSHAN ; Chou, Nan-Chi ; Suaris, Peter ; Chung-kuan Cheng

  • Volume
    26
  • Issue
    5
  • fYear
    2006
  • fDate
    5/1/2006 12:00:00 AM
  • Firstpage
    959
  • Lastpage
    969
  • Abstract
    We improve the efficiency of static timing analysis when false paths are considered. The efficiency of timing analysis is critical for the performance driven optimization program because timing analysis is invoked heavily in the inner loop. However, when false paths are dealt with in timing analysis, a large number of tags needs to be created and propagated, thus deteriorating efficiency. In this paper, we minimize the number of the tags through a biclique-covering approach, which iteratively removes a tag if the false path information in the tag is covered by the union of other tags. With the produced tags, we remove the false path timing and guarantee to cover the nonfalse path timing. Since the minimum biclique covering of the general bipartite graph is NP complete [ Indag. Math., vol. 39, p. 211, 1977], [ Discrete Math., vol. 149, no. 1-3, p. 159, 1996], we use a minimal degree ordering approach to perform the biclique-covering minimization. The experimental results show significant reduction on the number of tags
  • Keywords
    circuit analysis computing; circuit optimisation; directed graphs; minimisation; timing; NP complete; biclique covering minimization; bipartite graph; driven optimization program; false path timing; false subgraphs; known false paths; minimal degree ordering approach; static timing analysis; Algorithm design and analysis; Bipartite graph; Circuit optimization; Computer graphics; Computer science; Object detection; Performance analysis; Timing; Biclique covering; false subgraphs; static timing analysis;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2006.885737
  • Filename
    4193571