Title :
A 30-MHz trellis codec chip for partial-response channels
Author :
Shung, C. Bernard ; Siegel, Paul H. ; Thapar, Hemant K. ; Karabed, Razmik
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
12/1/1991 12:00:00 AM
Abstract :
The authors present a rate 8/10 matched-spectral-null (MSN) trellis codec chip which can increase noise tolerance in partial-response channels applicable to digital magnetic recording. The Viterbi detector in this codec features an area-efficient pipelined architecture and a modulo metric normalization technique. The chip was implemented in a 1.2-μm CMOS process with a die size of 22 mm2 . It offers a 12-Mb/s data rate when operating at 30 MHz. Experimental results verified the predicted coding gain of 2.8 dB relative to the uncoded system at a bit-error rate of 10-7
Keywords :
CMOS integrated circuits; VLSI; codecs; digital signal processing chips; magnetic recording; 1.2 micron; 12 Mbit/s; 2.8 dB; 30 MHz; CMOS process; DSP chips; Viterbi detector; area-efficient pipelined architecture; bit-error rate; coding gain; data rate; die size; digital magnetic recording; matched spectral null code; modulo metric normalization technique; partial-response channels; trellis code; trellis codec chip; Codecs; Convolutional codes; Decoding; Detectors; Frequency; Magnetic noise; Partial response channels; Polynomials; Transfer functions; Viterbi algorithm;
Journal_Title :
Solid-State Circuits, IEEE Journal of
