A 200 MHz CMOS pipelined multiplier-accumulator using a quasi-domino dynamic full-adder cell design

A bit-level pipelined 12 b×12 b two´s complement multiplier with a 27 b accumulator has been designed and fabricated in 1.0 μm p-well CMOS technology. A new quasi N-P domino logic structure has been adopted to increase the throughput rate, and special pipeline structures were used in the accumulator to reduce the total latency. The chip complexity is approximately 10000 transistors and the die area is 2.5 mm×3.7 mm. The measured maximum clock rate is 200 MHz (i.e. 200 million multiply-accumulate operations per second), and the power-speed ratio is 6.5 mW/MHz. A unique output buffer design was also adopted to achieve 200 MHz off-chip communication while maintaining full CMOS logic levels