A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme

Author

Wang, Chua-Chin ; Lee, Ching-Li ; Lin, Wun-Ji

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung

Volume

54

Issue

5

fYear

2007

fDate

5/1/2007 12:00:00 AM

Firstpage

1069

Lastpage

1076

Abstract

The physical implementation of a prototypical 250-MHz CMOS 4-T SRAM is described in this paper. The proposed SRAM cell takes advantage of a negative word-line scheme to minimize the leakage current of the cell access transistors. As a result, the standby power consumption is drastically reduced. The proposed 4-kb 4-T SRAM is measured to consume 0.32 mW in the standby mode, and a 3.8-ns access time in the R/W mode. The highest operating clock rate is measured to be 263 MHz

Keywords

CMOS memory circuits; SRAM chips; leakage currents; low-power electronics; memory architecture; power consumption; transistors; 0.32 mW; 250 MHz; 263 MHz; 3.8 ns; 4 kbit; CMOS 4-T SRAM; cell access transistors; leakage current; low-power SRAM design; negative word-line scheme; power-delay product; standby power consumption; CMOS digital integrated circuits; CMOS logic circuits; CMOS memory circuits; CMOS process; CMOS technology; Energy consumption; Leakage current; Logic arrays; Random access memory; Threshold voltage; 4-T SRAM cell; Leakage current; SRAM; negative word-line (NWL); power-delay product;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2006.888767

Filename

4195650