Title :
Temperature effects on trigate SOI MOSFETs
Author :
Colinge, Jean-Pierre ; Floyd, Liam ; Quinn, Aidan J. ; Redmond, Gareth ; Alderman, John C. ; Xiong, W. ; Cleavelin, C. Rinn ; Schulz, T. ; Schruefer, Klaus ; Knoblinger, Gerhard ; Patruno, Paul
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of California, Davis, CA, USA
fDate :
3/1/2006 12:00:00 AM
Abstract :
Trigate silicon-on-insulator (SOI) MOSFETs have been measured in the 5-400 K temperature range. The device fin width and height is 45 and 82 nm, respectively, and the p-type doping concentration in the channel is 6×1017 cm-3. The subthreshold slope varies linearly with temperature as predicted by fully depleted SOI MOS theory. The mobility is phonon limited for temperatures larger than 100 K, while it is limited by surface roughness below that temperature. The corner effect, in which the device corners have a lower threshold voltage than the top and sidewall Si/SiO2 interfaces, shows up at temperatures lower than 150 K.
Keywords :
MOSFET; semiconductor device measurement; silicon compounds; silicon-on-insulator; 45 nm; 5 to 400 K; 82 nm; MOSFET; Si-SiO2; cryogenic electronics; semiconductor device measurements; silicon-on-insulator technology; surface roughness; temperature effects; Doping; Etching; MOSFETs; Phonons; Rough surfaces; Semiconductor films; Silicon on insulator technology; Surface roughness; Temperature distribution; Threshold voltage; Cryogenic electronics; MOSFETs; quantum wires; semiconductor device measurements; silicon-on-insulator (SOI) technology;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2006.869941
