An assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature

Author

Lee, Wei ; Su, Pin ; Chen, Hou Yu ; Chang, Chang Yun ; Su, Ke Wei ; Liu, Sally ; Yang, Fu Liang

Author_Institution

Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

Volume

27

Issue

3

fYear

2006

fDate

3/1/2006 12:00:00 AM

Firstpage

182

Lastpage

184

Abstract

This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOSFETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 meV for devices with 30-nm gate length, may be modulated by the gate geometry. The multiple-gate SOI MOSFET, with its main advantage in the suppression of short-channel effects for CMOS scaling, presents a very promising scheme to build room-temperature single-electron transistors with standard silicon nanoelectronics process.

Keywords

MOSFET; nanoelectronics; silicon-on-insulator; single electron transistors; 1.6 nm; CMOS scaling; Coulomb blockade oscillations; charging energy; gate geometry; room temperature; short-channel effects; silicon nanoelectronics process; single electron transistors; single-electron effects; ultrashort multiple-gate SOI MOSFET; CMOS process; Geometry; Large-scale systems; Low power electronics; MOSFETs; Nanoelectronics; Silicon on insulator technology; Single electron transistors; Temperature; Tunneling; CMOS; coulomb blockade oscillation; multiple gate; silicon-on-insulator (SOI); single-electron effect; single-electron transistor;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2006.870240

Filename

1599473