A CMOS Class-D Line Driver Employing a Phase-Locked Loop Based PWM Generator

A Class-D line driver that utilizes a phase-locked loop (PLL) for PWM generation is presented. The principle of operation and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130 nm CMOS process. The amplifier can deliver 1.2 W into a 6.8 Ω load with a 4.8 V power supply. The architecture eliminates the requirements for a high-quality carrier generator and a high-speed voltage comparator that are often required in PWM implementations. It can achieve a THD of -65 dB, for a sinusoidal input with a frequency of 60 kHz, while employing a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W for a switching frequency of 10 MHz. The die area is 2.25 mm².