5.25 GHz CMOS cascode power amplifier for 802.11a wireless local area network

The authors investigate a 5.25 GHz highly integrated CMOS class-AB power amplifier for IEEE 802.11a wireless local area network. The proposed power amplifier is implemented with a two gain-stage structure which is followed by an off-chip output matching circuit. Moreover, transistor-level compensation techniques are employed to improve the linearity. The power amplifier is designed with an on-chip input matching circuit, whereas the output matching circuit translates the signal power from 50 to 20 Omega load resistance. The measured results indicate over 20% power-added efficiency, over 20 dBm output power and 28.6 dBm output IP3. All the specifications are based on 50 Omega input impedance at 2.4 V supply voltage.