• DocumentCode
    846333
  • Title

    Design of cascaded ECL gates with power constraint

  • Author

    Alioto, M. ; Grasso, A.D. ; Palumbo, G.

  • Author_Institution
    Dipt. di Ingegneria dell´´Informazione, Univ. di Siena, Italy
  • Volume
    42
  • Issue
    4
  • fYear
    2006
  • Firstpage
    211
  • Lastpage
    213
  • Abstract
    A design strategy to optimise the bias currents of low-power cascaded emitter coupled logic (ECL) gates is discussed. The results can be applied when a power constraint is assigned, and the available current per gate is much lower than the value which minimises the propagation delay. The strategy is independent of the process used and is suitable for hand calculations, avoiding the trial-and-error approach based on simulations. Design examples based on a 20 GHz bipolar process are also given.
  • Keywords
    bipolar logic circuits; cascade networks; delays; emitter-coupled logic; logic design; low-power electronics; 20 GHz; bias currents; bipolar process; low-power cascaded emitter coupled logic gates; power constraint; propagation delay;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20064002
  • Filename
    1599633
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=846333