A functional fault model for sequential machines

Author

Cheng, Kwang-Ting ; Jou, Jing-yang

Author_Institution

AT&T Bell Lab., Murray Hill, NJ, USA

Volume

11

Issue

9

fYear

1992

fDate

9/1/1992 12:00:00 AM

Firstpage

1065

Lastpage

1073

Abstract

A fault model at the state transition level is proposed for finite state machines. In this model, a fault causes the destination state of a state transition to be faulty. Analysis shows that a test set that detects all single-state-transition (SST) faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. The quality of the test set generated for SST faults is close to that of the sequences derived from the checking experiment. It is also shown that the upper bound of the length of the SST fault test is 2 MN² for an N-state M-transition machine, while that of the checking sequence is exponential. An automatic test generation algorithm and a test generation system, FTG, based on the model show that the test set generated for SST faults achieves high single stuck-at-fault coverage as well as high transistor fault coverage for multilevel implementations of the machine

Keywords

fault location; finite state machines; logic testing; checking sequence; finite state machines; functional fault model; multilevel implementations; multiple-state-transition; sequential machines; single-state-transition; state transition level; stuck-at-fault coverage; test generation algorithm; transistor fault coverage; upper bound; Automata; Automatic testing; Circuit faults; Circuit testing; Fault detection; Helium; Sequential analysis; Sequential circuits; System testing; Upper bound;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.159992

Filename

159992