• DocumentCode
    847048
  • Title

    A New Capacitorless 1T DRAM Cell: Surrounding Gate MOSFET With Vertical Channel (SGVC Cell)

  • Author

    Jeong, Hoon ; Song, Ki-Whan ; Park, Il Han ; Kim, Tae-Hun ; Lee, Yeun Seung ; Kim, Seong-Goo ; Seo, Jun ; Cho, Kyoungyong ; Lee, Kangyoon ; Shin, Hyungcheol ; Lee, Jong Duk ; Park, Byung-Gook

  • Author_Institution
    Sch. of Electr. Eng., Seoul Nat. Univ.
  • Volume
    6
  • Issue
    3
  • fYear
    2007
  • fDate
    5/1/2007 12:00:00 AM
  • Firstpage
    352
  • Lastpage
    357
  • Abstract
    We propose a surrounding gate MOSFET with vertical channel (SGVC cell) as a 1T DRAM cell. To confirm the memory operation of the SGVC cell, we simulated its memory effect and fabricated the highly scalable SGVC cell. According to simulation and measurement results, the SGVC cell can operate as a 1T DRAM having a sufficiently large sensing margin. Also, due to its vertical channel structure and common source architecture, it can readily be made into a 4F2 cell array
  • Keywords
    DRAM chips; MOSFET; semiconductor device measurement; SGVC cell; capacitorless 1T DRAM cell; gate MOSFET; memory effect; vertical channel structure; Capacitors; Costs; Current measurement; Impact ionization; MOSFET circuits; Random access memory; Research and development; Scalability; Silicon; Substrates; 1T DRAM cell; Memory effect; sensing margin; surrounding gate; vertical channel;
  • fLanguage
    English
  • Journal_Title
    Nanotechnology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1536-125X
  • Type

    jour

  • DOI
    10.1109/TNANO.2007.893575
  • Filename
    4200730
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=847048