• DocumentCode
    847646
  • Title

    Detection of bridging faults in programmable logic arrays

  • Author

    Saluja, K.K. ; Liu, C.-Y. ; Reddy, S.M.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
  • Volume
    28
  • Issue
    13
  • fYear
    1992
  • fDate
    6/18/1992 12:00:00 AM
  • Firstpage
    1226
  • Lastpage
    1228
  • Abstract
    A test set and a testable design for MOS PLAs are proposed. The new design, which modifies a PLA by adding one extra line in the AND plane and one extra line in the OR plane, can detect bridging faults. Furthermore, the design modification requires very low area overhead and is independent of the personality of the PLA under test.
  • Keywords
    MOS integrated circuits; fault location; integrated circuit testing; logic arrays; logic design; logic testing; AND plane; MOS PLAs; OR plane; bridging faults; programmable logic arrays; test set; testable design;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19920774
  • Filename
    144350
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=847646