An Investigation of Fast Low Power Charge Sensitive Preamplifier Design

As nuclear measurement instrumentation becomes more and more sophisticated, there is an increased interest in reducing the rise time in charge sensitive preamplifiers, e. g., to allow precision spectroscopy with narrow pulse shaping or to reduce jitter in timing measurements. For charge sensitive amplifiers with a FET input, the phase shift produced in the FET is found to approximate a delay which is seen to be the most significant limitation on the amplifier closed loop bandwidth. Loop stability constraints limit the achievable rise time to 1 to 2 times the overall loop delay which can approach that of the FET. Three design approaches and circuit examples are given using one, two, and three voltage gain stages preceding an output buffer.