DocumentCode
84856
Title
Corrections to “Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction” [Mar 15 534-543]
Author
Joshi, Rajiv V. ; Kanj, Rouwaida
Author_Institution
, IBM T. J. Watson Laboratories, Yorktown Heights, NY, USA
Volume
23
Issue
7
fYear
2015
fDate
Jul-15
Firstpage
1380
Lastpage
1380
Abstract
On [1, p. 536] , Section II-A, second paragraph, lines 5–8, [2] should be used instead of [1] and the correct statement is as follows. “Model-to-hardware corroboration shows an excellent matching between importance-sampling-based methods yield estimation [2] and the true hardware yield. We therefore adopt the methodology in [2] as the core statistical engine for our TfM methodology.”
Keywords
Capacitance; FinFETs; Mixed analog digital integrated circuits; SRAM chips; Statistical analysis; Yield estimation;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2015.2429293
Filename
7115956
Link To Document