A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations

Author

Sridharan, K. ; Priya, T.K.

Author_Institution

Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore

Volume

54

Issue

3

fYear

2007

fDate

6/1/2007 12:00:00 AM

Firstpage

1800

Lastpage

1804

Abstract

The reduced visibility graph (RVG) is an important structure for computation of shortest paths for mobile robots. An efficient bit representation is proposed to construct segments that are part of the RVG. Based on the bit representation, a hardware-efficient scheme is presented whose computational complexity is O(k²log(n/k)), where k is the number of objects and n is the total number of vertices. An architecture that accomplishes the construction of the RVG without division or explicit intersection point calculations is proposed. An efficient field-programmable gate array implementation using block random access memory on an XCV3200E device is presented

Keywords

field programmable gate arrays; graphs; mobile robots; random-access storage; FPGA realization; RVG; block random access memory; efficient bit representations; field-programmable gate array; hardware accelerator; hardware-efficient scheme; mobile robots; reduced visibility graph; Adaptive control; Computational complexity; Computer architecture; Field programmable gate arrays; Hardware; Mobile robots; Motion planning; Random access memory; Robotics and automation; Temperature control; Efficient bit representation; field-programmable gate array (FPGA) implementation; hardware accelerator; reduced visibility graph (RVG); robotics;

fLanguage

English

Journal_Title

Industrial Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0278-0046

Type

jour

DOI

10.1109/TIE.2007.894726

Filename

4200886