Title :
Fast signature computation for BIST linear compactors
Author :
Lambidonis, D. ; Ivanov, A. ; Agarwal, V.K.
Author_Institution :
Radio Aids Group, CAE Electron. Ltd., Montreal, Que., Canada
fDate :
8/1/1995 12:00:00 AM
Abstract :
Signature computation for linear compactors in a BIST environment is a computationally intensive process. In this paper, a fast compaction simulation algorithm is presented which uses superposition and look-up tables. While keeping memory requirements reasonable, this algorithm has a speedup advantage of at least one order of magnitude over traditional algorithms, and offers a threefold speedup over recently published “fast” algorithms. Our algorithm is also applicable to any linear compactor - while existing algorithms are restricted to only one type of compactor. Simulation results comparing the speed and memory requirements of the proposed compaction algorithm to that of existing compaction algorithms are given
Keywords :
automatic test software; binary sequences; built-in self test; computational complexity; integrated circuit testing; logic testing; table lookup; BIST linear compactors; fast compaction simulation algorithm; fast signature computation; lookup tables; memory requirements; superposition; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Compaction; Computational modeling; Computer simulation; Data communication; Measurement standards; Quantum computing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on